
PIC16F946
DS41265A-page 180
Preliminary
2005 Microchip Technology Inc.
FIGURE 14-11:
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SD
A
SC
L
S
SPI
F
B
F
(
S
SPST
A
T
<0
>)
S
1
2
3
4
5
6
78
9
123
4
5
6
7
8
9
1
2
3
4
5
789
P
1
0
A
9
A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
1
0
A
8
R/W
=
1
ACK
R/
W
=
0
ACK
R
e
c
e
iv
e
Fi
rs
tB
y
te
of
A
d
dr
e
s
Cle
a
re
d
in
so
ft
wa
re
Bu
s
m
a
s
te
r
te
rm
in
at
e
s
tr
an
sfer
A9
6
(P
IR
1<
3
>
)
R
e
ce
iv
e
S
e
cond
B
y
te
of
A
d
dr
ess
C
le
a
red
by
har
dw
a
re
w
hen
SSP
ADD
is
u
p
d
a
te
d
with
lo
w
by
te
o
fad
dr
e
s
UA
(
S
SPST
A
T
<1
>)
Clo
ck
is
h
e
ld
lo
w
u
n
til
up
dat
e
of
S
P
A
D
h
a
s
ta
ken
pl
ace
UA
is
s
e
tin
d
ica
ti
n
g
th
at
t
he
S
P
A
D
ne
ed
s
to
be
upd
ate
d
UA
is
se
tin
d
ic
a
tin
g
th
a
tSSP
ADD
n
e
d
s
to
b
e
u
pda
ted
C
lear
ed
by
h
a
rd
w
a
re
w
h
en
SS
P
A
DD
is
u
p
d
a
te
d
with
h
ig
h
byte
of
add
re
ss
SSP
BUF
is
wr
it
te
n
w
it
h
cont
ents
o
f
Du
m
y
r
e
a
d
o
fSSPBUF
to
clea
rB
F
flag
R
e
c
e
iv
e
Fi
rs
tB
y
te
of
A
d
dr
e
s
12
3
4
5
7
89
D7
D6
D5
D4
D3
D1
ACK
D2
6
T
ra
n
sm
itting
Data
B
y
te
D0
Du
m
y
r
e
a
d
o
fSSPBUF
to
clea
rB
F
flag
Sr
C
lear
ed
i
n
so
ftw
a
re
W
rit
e
o
fSSPBUF
in
itia
te
s
t
ra
n
sm
it
C
le
a
red
i
n
so
ftw
ar
e
C
o
m
p
le
ti
on
of
clea
rs
B
F
fla
g
C
K
P
(
S
P
CO
N<4
>
)
CK
P
is
set
in
so
ftwar
e
C
K
P
i
s
aut
oma
ti
c
al
ly
cl
ear
ed
i
n
h
a
rd
w
a
re
Clo
ck
is
h
e
ld
lo
w
u
n
til
u
pda
te
o
fS
S
P
A
D
has
ta
k
e
n
p
lac
e
da
ta
tr
a
n
sm
ission
Clo
ck
is
h
e
ld
lo
w
u
n
ti
l
CKP
is
se
tto
‘1
’
B
F
f
lag
i
s
cl
ea
r
thi
rd
a
ddr
ess
sequ
en
ce
at
the
end
of
the
h
o
ld
in
g
SCL
lo
w
SSP
SR